Advanced Configuration and Power Interface Specification (ACPI), Revision 2.0, Compaq Computer Corporation, Intel Corporation, Microsoft Corporation, Phoenix Technologies Ltd. and Toshiba Corporation, published Jul. 27, 2000, describes an interaction between computing hardware and software. In computing devices that comply with the ACPI specification, the hardware notifies the software, in particular the operating system (OS) executing on the computing device of runtime events, such as, e.g., when a device is plugged into the computing device while still powered on. This is colloquially referred to as hot plugging, which is a type of runtime general purpose event.
Most computing devices have specialized components for handling general purpose events and for notifying the ACPI OS. These specialized components, which are typically part of a bus bridge or input/output (I/O) controller within the computing device architecture, have inputs or side-band signals, called general purpose inputs, with which other components of the computing device can signal a general purpose event. When a general purpose input is asserted, a System Control Interrupt (SCI) is generated to notify the ACPI OS. The general purpose input is typically latched, because the ACPI OS must determine the cause of the SCI to correctly identify the event.
FIG. 1 is a block diagram of a conventional computing architecture for detecting and communicating such general purpose events. As shown, computing device 100 includes processor(s) 102, host controller 104, memory 106, I/O controller 108, bus 110, bridge 112, general purpose input 114, bridge device 116, and device 118, each logically coupled as shown. I/O controller 108 is capable of generating an SCI to notify the ACPI OS of a general purpose event. Bridge 112 is capable of detecting a hot plug of bridge device 116, and bridge 112 will notify I/O controller 108 of such a hot plug by asserting general purpose input 114.
The need for general purpose input 114 limits computing device 100 in that wherever bridge 112 is located, an additional wire is needed to couple bridge 112 with I/O controller 108. This doesn't present a significant problem when bridge 112 is located within the same case or chassis as I/O controller 108, however it would present a problem if bridge 112 where to located in a separate case or chassis from I/O controller 108. Further, for every bridge that supports hot plug of devices present in the system (such as bridge 112), it requires a corresponding sideband signal (such as 114). This adds to the cost, complexity and in general introduces a scalability problem for the platform.